module DRAM(
    input clk,
    input dram_we,
    input [31:0] adr,
    input [31:0] wdin,
    input [23:0] io_sw,

    output reg [23:0] io_led,
    output reg [31:0] rd
    
    );

    assign ram_clk = !clk;
    
    // if write led
    always @(*) begin
        if(adr == 32'hFFFF_F060)         we = 1'b0;
        else                             we = dram_we;
    end
    
    // write led
    always @(*) begin
        if(adr == 32'hFFFF_F060 && dram_we)      io_led = wdin[23:0];
        else                                     io_led = io_led;
    end
    
    // read sw and btn
    always @(*) begin
        if(adr == 32'hFFFF_F070)         rd = {8'b0,  io_sw[23:0]};    
        else                             rd = tmp_rd;
    end

    // connect with dram
    reg we; 
    wire [31:0] tmp_rd; 
    
    dram U_dram (
        .clk    (ram_clk),
        .a      (adr[15:2]),
        .spo    (tmp_rd),
        .we     (we),
        .d      (wdin)
    );
    
endmodule
